Update dependencies and build to go1.22 (#2113)
* Update dependencies and build to go1.22 * Fix api changes wrt to dependencies * Update golangci config
This commit is contained in:
Wim
28
vendor/github.com/klauspost/cpuid/v2/README.md
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vendor/github.com/klauspost/cpuid/v2/README.md
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@@ -9,16 +9,19 @@ You can access the CPU information by accessing the shared CPU variable of the c
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Package home: https://github.com/klauspost/cpuid
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[](https://pkg.go.dev/github.com/klauspost/cpuid/v2)
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[![Build Status][3]][4]
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[3]: https://travis-ci.org/klauspost/cpuid.svg?branch=master
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[4]: https://travis-ci.org/klauspost/cpuid
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[](https://github.com/klauspost/cpuid/actions/workflows/go.yml)
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## installing
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`go get -u github.com/klauspost/cpuid/v2` using modules.
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Drop `v2` for others.
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Installing binary:
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`go install github.com/klauspost/cpuid/v2/cmd/cpuid@latest`
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Or download binaries from release page: https://github.com/klauspost/cpuid/releases
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### Homebrew
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For macOS/Linux users, you can install via [brew](https://brew.sh/)
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@@ -279,7 +282,12 @@ Exit Code 1
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| AMXINT8 | Tile computational operations on 8-bit integers |
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| AMXFP16 | Tile computational operations on FP16 numbers |
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| AMXTILE | Tile architecture |
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| APX_F | Intel APX |
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| AVX | AVX functions |
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| AVX10 | If set the Intel AVX10 Converged Vector ISA is supported |
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| AVX10_128 | If set indicates that AVX10 128-bit vector support is present |
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| AVX10_256 | If set indicates that AVX10 256-bit vector support is present |
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| AVX10_512 | If set indicates that AVX10 512-bit vector support is present |
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| AVX2 | AVX2 functions |
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| AVX512BF16 | AVX-512 BFLOAT16 Instructions |
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| AVX512BITALG | AVX-512 Bit Algorithms |
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@@ -302,6 +310,7 @@ Exit Code 1
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| AVXSLOW | Indicates the CPU performs 2 128 bit operations instead of one |
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| AVXVNNI | AVX (VEX encoded) VNNI neural network instructions |
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| AVXVNNIINT8 | AVX-VNNI-INT8 instructions |
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| BHI_CTRL | Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598 |
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| BMI1 | Bit Manipulation Instruction Set 1 |
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| BMI2 | Bit Manipulation Instruction Set 2 |
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| CETIBT | Intel CET Indirect Branch Tracking |
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@@ -355,8 +364,11 @@ Exit Code 1
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| IBS_OPFUSE | AMD: Indicates support for IbsOpFuse |
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| IBS_PREVENTHOST | Disallowing IBS use by the host supported |
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| IBS_ZEN4 | Fetch and Op IBS support IBS extensions added with Zen4 |
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| IDPRED_CTRL | IPRED_DIS |
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| INT_WBINVD | WBINVD/WBNOINVD are interruptible. |
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| INVLPGB | NVLPGB and TLBSYNC instruction supported |
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| KEYLOCKER | Key locker |
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| KEYLOCKERW | Key locker wide |
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| LAHF | LAHF/SAHF in long mode |
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| LAM | If set, CPU supports Linear Address Masking |
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| LBRVIRT | LBR virtualization |
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@@ -374,6 +386,7 @@ Exit Code 1
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| MPX | Intel MPX (Memory Protection Extensions) |
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| MOVU | MOVU SSE instructions are more efficient and should be preferred to SSE MOVL/MOVH. MOVUPS is more efficient than MOVLPS/MOVHPS. MOVUPD is more efficient than MOVLPD/MOVHPD |
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| MSRIRC | Instruction Retired Counter MSR available |
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| MSRLIST | Read/Write List of Model Specific Registers |
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| MSR_PAGEFLUSH | Page Flush MSR available |
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| NRIPS | Indicates support for NRIP save on VMEXIT |
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| NX | NX (No-Execute) bit |
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@@ -381,12 +394,13 @@ Exit Code 1
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| PCONFIG | PCONFIG for Intel Multi-Key Total Memory Encryption |
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| POPCNT | POPCNT instruction |
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| PPIN | AMD: Protected Processor Inventory Number support. Indicates that Protected Processor Inventory Number (PPIN) capability can be enabled |
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| PREFETCHI | PREFETCHIT0/1 instructions |
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| PSFD | AMD: Predictive Store Forward Disable |
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| PREFETCHI | PREFETCHIT0/1 instructions |
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| PSFD | Predictive Store Forward Disable |
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| RDPRU | RDPRU instruction supported |
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| RDRAND | RDRAND instruction is available |
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| RDSEED | RDSEED instruction is available |
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| RDTSCP | RDTSCP Instruction |
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| RRSBA_CTRL | Restricted RSB Alternate |
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| RTM | Restricted Transactional Memory |
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| RTM_ALWAYS_ABORT | Indicates that the loaded microcode is forcing RTM abort. |
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| SERIALIZE | Serialize Instruction Execution |
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@@ -425,6 +439,7 @@ Exit Code 1
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| SYSCALL | System-Call Extension (SCE): SYSCALL and SYSRET instructions. |
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| SYSEE | SYSENTER and SYSEXIT instructions |
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| TBM | AMD Trailing Bit Manipulation |
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| TDX_GUEST | Intel Trust Domain Extensions Guest |
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| TLB_FLUSH_NESTED | AMD: Flushing includes all the nested translations for guest translations |
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| TME | Intel Total Memory Encryption. The following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE, IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE. |
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| TOPEXT | TopologyExtensions: topology extensions support. Indicates support for CPUID Fn8000_001D_EAX_x[N:0]-CPUID Fn8000_001E_EDX. |
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@@ -439,6 +454,7 @@ Exit Code 1
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| VTE | AMD Virtual Transparent Encryption supported |
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| WAITPKG | TPAUSE, UMONITOR, UMWAIT |
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| WBNOINVD | Write Back and Do Not Invalidate Cache |
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| WRMSRNS | Non-Serializing Write to Model Specific Register |
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| X87 | FPU |
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| XGETBV1 | Supports XGETBV with ECX = 1 |
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| XOP | Bulldozer XOP functions |
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477
vendor/github.com/klauspost/cpuid/v2/cpuid.go
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vendor/github.com/klauspost/cpuid/v2/cpuid.go
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@@ -67,182 +67,200 @@ const (
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// Keep index -1 as unknown
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UNKNOWN = -1
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// Add features
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ADX FeatureID = iota // Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
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AESNI // Advanced Encryption Standard New Instructions
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AMD3DNOW // AMD 3DNOW
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AMD3DNOWEXT // AMD 3DNowExt
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AMXBF16 // Tile computational operations on BFLOAT16 numbers
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AMXFP16 // Tile computational operations on FP16 numbers
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AMXINT8 // Tile computational operations on 8-bit integers
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AMXTILE // Tile architecture
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AVX // AVX functions
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AVX2 // AVX2 functions
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AVX512BF16 // AVX-512 BFLOAT16 Instructions
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AVX512BITALG // AVX-512 Bit Algorithms
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AVX512BW // AVX-512 Byte and Word Instructions
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AVX512CD // AVX-512 Conflict Detection Instructions
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AVX512DQ // AVX-512 Doubleword and Quadword Instructions
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AVX512ER // AVX-512 Exponential and Reciprocal Instructions
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AVX512F // AVX-512 Foundation
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AVX512FP16 // AVX-512 FP16 Instructions
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AVX512IFMA // AVX-512 Integer Fused Multiply-Add Instructions
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AVX512PF // AVX-512 Prefetch Instructions
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AVX512VBMI // AVX-512 Vector Bit Manipulation Instructions
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AVX512VBMI2 // AVX-512 Vector Bit Manipulation Instructions, Version 2
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AVX512VL // AVX-512 Vector Length Extensions
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AVX512VNNI // AVX-512 Vector Neural Network Instructions
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AVX512VP2INTERSECT // AVX-512 Intersect for D/Q
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AVX512VPOPCNTDQ // AVX-512 Vector Population Count Doubleword and Quadword
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AVXIFMA // AVX-IFMA instructions
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AVXNECONVERT // AVX-NE-CONVERT instructions
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AVXSLOW // Indicates the CPU performs 2 128 bit operations instead of one
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AVXVNNI // AVX (VEX encoded) VNNI neural network instructions
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AVXVNNIINT8 // AVX-VNNI-INT8 instructions
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BMI1 // Bit Manipulation Instruction Set 1
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BMI2 // Bit Manipulation Instruction Set 2
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CETIBT // Intel CET Indirect Branch Tracking
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CETSS // Intel CET Shadow Stack
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CLDEMOTE // Cache Line Demote
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CLMUL // Carry-less Multiplication
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CLZERO // CLZERO instruction supported
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CMOV // i686 CMOV
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CMPCCXADD // CMPCCXADD instructions
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CMPSB_SCADBS_SHORT // Fast short CMPSB and SCASB
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CMPXCHG8 // CMPXCHG8 instruction
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CPBOOST // Core Performance Boost
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CPPC // AMD: Collaborative Processor Performance Control
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CX16 // CMPXCHG16B Instruction
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EFER_LMSLE_UNS // AMD: =Core::X86::Msr::EFER[LMSLE] is not supported, and MBZ
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ENQCMD // Enqueue Command
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ERMS // Enhanced REP MOVSB/STOSB
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F16C // Half-precision floating-point conversion
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FLUSH_L1D // Flush L1D cache
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FMA3 // Intel FMA 3. Does not imply AVX.
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FMA4 // Bulldozer FMA4 functions
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FP128 // AMD: When set, the internal FP/SIMD execution datapath is no more than 128-bits wide
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FP256 // AMD: When set, the internal FP/SIMD execution datapath is no more than 256-bits wide
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FSRM // Fast Short Rep Mov
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FXSR // FXSAVE, FXRESTOR instructions, CR4 bit 9
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FXSROPT // FXSAVE/FXRSTOR optimizations
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GFNI // Galois Field New Instructions. May require other features (AVX, AVX512VL,AVX512F) based on usage.
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HLE // Hardware Lock Elision
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HRESET // If set CPU supports history reset and the IA32_HRESET_ENABLE MSR
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HTT // Hyperthreading (enabled)
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HWA // Hardware assert supported. Indicates support for MSRC001_10
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HYBRID_CPU // This part has CPUs of more than one type.
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HYPERVISOR // This bit has been reserved by Intel & AMD for use by hypervisors
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IA32_ARCH_CAP // IA32_ARCH_CAPABILITIES MSR (Intel)
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IA32_CORE_CAP // IA32_CORE_CAPABILITIES MSR
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IBPB // Indirect Branch Restricted Speculation (IBRS) and Indirect Branch Predictor Barrier (IBPB)
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IBRS // AMD: Indirect Branch Restricted Speculation
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IBRS_PREFERRED // AMD: IBRS is preferred over software solution
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IBRS_PROVIDES_SMP // AMD: IBRS provides Same Mode Protection
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IBS // Instruction Based Sampling (AMD)
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IBSBRNTRGT // Instruction Based Sampling Feature (AMD)
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IBSFETCHSAM // Instruction Based Sampling Feature (AMD)
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IBSFFV // Instruction Based Sampling Feature (AMD)
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IBSOPCNT // Instruction Based Sampling Feature (AMD)
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IBSOPCNTEXT // Instruction Based Sampling Feature (AMD)
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IBSOPSAM // Instruction Based Sampling Feature (AMD)
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IBSRDWROPCNT // Instruction Based Sampling Feature (AMD)
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IBSRIPINVALIDCHK // Instruction Based Sampling Feature (AMD)
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IBS_FETCH_CTLX // AMD: IBS fetch control extended MSR supported
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IBS_OPDATA4 // AMD: IBS op data 4 MSR supported
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IBS_OPFUSE // AMD: Indicates support for IbsOpFuse
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IBS_PREVENTHOST // Disallowing IBS use by the host supported
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IBS_ZEN4 // AMD: Fetch and Op IBS support IBS extensions added with Zen4
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INT_WBINVD // WBINVD/WBNOINVD are interruptible.
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INVLPGB // NVLPGB and TLBSYNC instruction supported
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LAHF // LAHF/SAHF in long mode
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LAM // If set, CPU supports Linear Address Masking
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LBRVIRT // LBR virtualization
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LZCNT // LZCNT instruction
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MCAOVERFLOW // MCA overflow recovery support.
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MCDT_NO // Processor do not exhibit MXCSR Configuration Dependent Timing behavior and do not need to mitigate it.
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MCOMMIT // MCOMMIT instruction supported
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MD_CLEAR // VERW clears CPU buffers
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MMX // standard MMX
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MMXEXT // SSE integer functions or AMD MMX ext
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MOVBE // MOVBE instruction (big-endian)
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MOVDIR64B // Move 64 Bytes as Direct Store
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MOVDIRI // Move Doubleword as Direct Store
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MOVSB_ZL // Fast Zero-Length MOVSB
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MOVU // AMD: MOVU SSE instructions are more efficient and should be preferred to SSE MOVL/MOVH. MOVUPS is more efficient than MOVLPS/MOVHPS. MOVUPD is more efficient than MOVLPD/MOVHPD
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MPX // Intel MPX (Memory Protection Extensions)
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MSRIRC // Instruction Retired Counter MSR available
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MSR_PAGEFLUSH // Page Flush MSR available
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NRIPS // Indicates support for NRIP save on VMEXIT
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NX // NX (No-Execute) bit
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OSXSAVE // XSAVE enabled by OS
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PCONFIG // PCONFIG for Intel Multi-Key Total Memory Encryption
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POPCNT // POPCNT instruction
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PPIN // AMD: Protected Processor Inventory Number support. Indicates that Protected Processor Inventory Number (PPIN) capability can be enabled
|
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PREFETCHI // PREFETCHIT0/1 instructions
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PSFD // AMD: Predictive Store Forward Disable
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||||
RDPRU // RDPRU instruction supported
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RDRAND // RDRAND instruction is available
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RDSEED // RDSEED instruction is available
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RDTSCP // RDTSCP Instruction
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RTM // Restricted Transactional Memory
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||||
RTM_ALWAYS_ABORT // Indicates that the loaded microcode is forcing RTM abort.
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SERIALIZE // Serialize Instruction Execution
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SEV // AMD Secure Encrypted Virtualization supported
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SEV_64BIT // AMD SEV guest execution only allowed from a 64-bit host
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SEV_ALTERNATIVE // AMD SEV Alternate Injection supported
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SEV_DEBUGSWAP // Full debug state swap supported for SEV-ES guests
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SEV_ES // AMD SEV Encrypted State supported
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SEV_RESTRICTED // AMD SEV Restricted Injection supported
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SEV_SNP // AMD SEV Secure Nested Paging supported
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SGX // Software Guard Extensions
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SGXLC // Software Guard Extensions Launch Control
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SHA // Intel SHA Extensions
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SME // AMD Secure Memory Encryption supported
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SME_COHERENT // AMD Hardware cache coherency across encryption domains enforced
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SPEC_CTRL_SSBD // Speculative Store Bypass Disable
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SRBDS_CTRL // SRBDS mitigation MSR available
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SSE // SSE functions
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SSE2 // P4 SSE functions
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SSE3 // Prescott SSE3 functions
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SSE4 // Penryn SSE4.1 functions
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SSE42 // Nehalem SSE4.2 functions
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SSE4A // AMD Barcelona microarchitecture SSE4a instructions
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SSSE3 // Conroe SSSE3 functions
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STIBP // Single Thread Indirect Branch Predictors
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STIBP_ALWAYSON // AMD: Single Thread Indirect Branch Prediction Mode has Enhanced Performance and may be left Always On
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STOSB_SHORT // Fast short STOSB
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SUCCOR // Software uncorrectable error containment and recovery capability.
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SVM // AMD Secure Virtual Machine
|
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SVMDA // Indicates support for the SVM decode assists.
|
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SVMFBASID // SVM, Indicates that TLB flush events, including CR3 writes and CR4.PGE toggles, flush only the current ASID's TLB entries. Also indicates support for the extended VMCBTLB_Control
|
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SVML // AMD SVM lock. Indicates support for SVM-Lock.
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SVMNP // AMD SVM nested paging
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SVMPF // SVM pause intercept filter. Indicates support for the pause intercept filter
|
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SVMPFT // SVM PAUSE filter threshold. Indicates support for the PAUSE filter cycle count threshold
|
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SYSCALL // System-Call Extension (SCE): SYSCALL and SYSRET instructions.
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SYSEE // SYSENTER and SYSEXIT instructions
|
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TBM // AMD Trailing Bit Manipulation
|
||||
TLB_FLUSH_NESTED // AMD: Flushing includes all the nested translations for guest translations
|
||||
TME // Intel Total Memory Encryption. The following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE, IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE.
|
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TOPEXT // TopologyExtensions: topology extensions support. Indicates support for CPUID Fn8000_001D_EAX_x[N:0]-CPUID Fn8000_001E_EDX.
|
||||
TSCRATEMSR // MSR based TSC rate control. Indicates support for MSR TSC ratio MSRC000_0104
|
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TSXLDTRK // Intel TSX Suspend Load Address Tracking
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VAES // Vector AES. AVX(512) versions requires additional checks.
|
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VMCBCLEAN // VMCB clean bits. Indicates support for VMCB clean bits.
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VMPL // AMD VM Permission Levels supported
|
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VMSA_REGPROT // AMD VMSA Register Protection supported
|
||||
VMX // Virtual Machine Extensions
|
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VPCLMULQDQ // Carry-Less Multiplication Quadword. Requires AVX for 3 register versions.
|
||||
VTE // AMD Virtual Transparent Encryption supported
|
||||
WAITPKG // TPAUSE, UMONITOR, UMWAIT
|
||||
WBNOINVD // Write Back and Do Not Invalidate Cache
|
||||
X87 // FPU
|
||||
XGETBV1 // Supports XGETBV with ECX = 1
|
||||
XOP // Bulldozer XOP functions
|
||||
XSAVE // XSAVE, XRESTOR, XSETBV, XGETBV
|
||||
XSAVEC // Supports XSAVEC and the compacted form of XRSTOR.
|
||||
XSAVEOPT // XSAVEOPT available
|
||||
XSAVES // Supports XSAVES/XRSTORS and IA32_XSS
|
||||
// x86 features
|
||||
ADX FeatureID = iota // Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
|
||||
AESNI // Advanced Encryption Standard New Instructions
|
||||
AMD3DNOW // AMD 3DNOW
|
||||
AMD3DNOWEXT // AMD 3DNowExt
|
||||
AMXBF16 // Tile computational operations on BFLOAT16 numbers
|
||||
AMXFP16 // Tile computational operations on FP16 numbers
|
||||
AMXINT8 // Tile computational operations on 8-bit integers
|
||||
AMXTILE // Tile architecture
|
||||
APX_F // Intel APX
|
||||
AVX // AVX functions
|
||||
AVX10 // If set the Intel AVX10 Converged Vector ISA is supported
|
||||
AVX10_128 // If set indicates that AVX10 128-bit vector support is present
|
||||
AVX10_256 // If set indicates that AVX10 256-bit vector support is present
|
||||
AVX10_512 // If set indicates that AVX10 512-bit vector support is present
|
||||
AVX2 // AVX2 functions
|
||||
AVX512BF16 // AVX-512 BFLOAT16 Instructions
|
||||
AVX512BITALG // AVX-512 Bit Algorithms
|
||||
AVX512BW // AVX-512 Byte and Word Instructions
|
||||
AVX512CD // AVX-512 Conflict Detection Instructions
|
||||
AVX512DQ // AVX-512 Doubleword and Quadword Instructions
|
||||
AVX512ER // AVX-512 Exponential and Reciprocal Instructions
|
||||
AVX512F // AVX-512 Foundation
|
||||
AVX512FP16 // AVX-512 FP16 Instructions
|
||||
AVX512IFMA // AVX-512 Integer Fused Multiply-Add Instructions
|
||||
AVX512PF // AVX-512 Prefetch Instructions
|
||||
AVX512VBMI // AVX-512 Vector Bit Manipulation Instructions
|
||||
AVX512VBMI2 // AVX-512 Vector Bit Manipulation Instructions, Version 2
|
||||
AVX512VL // AVX-512 Vector Length Extensions
|
||||
AVX512VNNI // AVX-512 Vector Neural Network Instructions
|
||||
AVX512VP2INTERSECT // AVX-512 Intersect for D/Q
|
||||
AVX512VPOPCNTDQ // AVX-512 Vector Population Count Doubleword and Quadword
|
||||
AVXIFMA // AVX-IFMA instructions
|
||||
AVXNECONVERT // AVX-NE-CONVERT instructions
|
||||
AVXSLOW // Indicates the CPU performs 2 128 bit operations instead of one
|
||||
AVXVNNI // AVX (VEX encoded) VNNI neural network instructions
|
||||
AVXVNNIINT8 // AVX-VNNI-INT8 instructions
|
||||
BHI_CTRL // Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598
|
||||
BMI1 // Bit Manipulation Instruction Set 1
|
||||
BMI2 // Bit Manipulation Instruction Set 2
|
||||
CETIBT // Intel CET Indirect Branch Tracking
|
||||
CETSS // Intel CET Shadow Stack
|
||||
CLDEMOTE // Cache Line Demote
|
||||
CLMUL // Carry-less Multiplication
|
||||
CLZERO // CLZERO instruction supported
|
||||
CMOV // i686 CMOV
|
||||
CMPCCXADD // CMPCCXADD instructions
|
||||
CMPSB_SCADBS_SHORT // Fast short CMPSB and SCASB
|
||||
CMPXCHG8 // CMPXCHG8 instruction
|
||||
CPBOOST // Core Performance Boost
|
||||
CPPC // AMD: Collaborative Processor Performance Control
|
||||
CX16 // CMPXCHG16B Instruction
|
||||
EFER_LMSLE_UNS // AMD: =Core::X86::Msr::EFER[LMSLE] is not supported, and MBZ
|
||||
ENQCMD // Enqueue Command
|
||||
ERMS // Enhanced REP MOVSB/STOSB
|
||||
F16C // Half-precision floating-point conversion
|
||||
FLUSH_L1D // Flush L1D cache
|
||||
FMA3 // Intel FMA 3. Does not imply AVX.
|
||||
FMA4 // Bulldozer FMA4 functions
|
||||
FP128 // AMD: When set, the internal FP/SIMD execution datapath is no more than 128-bits wide
|
||||
FP256 // AMD: When set, the internal FP/SIMD execution datapath is no more than 256-bits wide
|
||||
FSRM // Fast Short Rep Mov
|
||||
FXSR // FXSAVE, FXRESTOR instructions, CR4 bit 9
|
||||
FXSROPT // FXSAVE/FXRSTOR optimizations
|
||||
GFNI // Galois Field New Instructions. May require other features (AVX, AVX512VL,AVX512F) based on usage.
|
||||
HLE // Hardware Lock Elision
|
||||
HRESET // If set CPU supports history reset and the IA32_HRESET_ENABLE MSR
|
||||
HTT // Hyperthreading (enabled)
|
||||
HWA // Hardware assert supported. Indicates support for MSRC001_10
|
||||
HYBRID_CPU // This part has CPUs of more than one type.
|
||||
HYPERVISOR // This bit has been reserved by Intel & AMD for use by hypervisors
|
||||
IA32_ARCH_CAP // IA32_ARCH_CAPABILITIES MSR (Intel)
|
||||
IA32_CORE_CAP // IA32_CORE_CAPABILITIES MSR
|
||||
IBPB // Indirect Branch Restricted Speculation (IBRS) and Indirect Branch Predictor Barrier (IBPB)
|
||||
IBPB_BRTYPE // Indicates that MSR 49h (PRED_CMD) bit 0 (IBPB) flushes all branch type predictions from the CPU branch predictor
|
||||
IBRS // AMD: Indirect Branch Restricted Speculation
|
||||
IBRS_PREFERRED // AMD: IBRS is preferred over software solution
|
||||
IBRS_PROVIDES_SMP // AMD: IBRS provides Same Mode Protection
|
||||
IBS // Instruction Based Sampling (AMD)
|
||||
IBSBRNTRGT // Instruction Based Sampling Feature (AMD)
|
||||
IBSFETCHSAM // Instruction Based Sampling Feature (AMD)
|
||||
IBSFFV // Instruction Based Sampling Feature (AMD)
|
||||
IBSOPCNT // Instruction Based Sampling Feature (AMD)
|
||||
IBSOPCNTEXT // Instruction Based Sampling Feature (AMD)
|
||||
IBSOPSAM // Instruction Based Sampling Feature (AMD)
|
||||
IBSRDWROPCNT // Instruction Based Sampling Feature (AMD)
|
||||
IBSRIPINVALIDCHK // Instruction Based Sampling Feature (AMD)
|
||||
IBS_FETCH_CTLX // AMD: IBS fetch control extended MSR supported
|
||||
IBS_OPDATA4 // AMD: IBS op data 4 MSR supported
|
||||
IBS_OPFUSE // AMD: Indicates support for IbsOpFuse
|
||||
IBS_PREVENTHOST // Disallowing IBS use by the host supported
|
||||
IBS_ZEN4 // AMD: Fetch and Op IBS support IBS extensions added with Zen4
|
||||
IDPRED_CTRL // IPRED_DIS
|
||||
INT_WBINVD // WBINVD/WBNOINVD are interruptible.
|
||||
INVLPGB // NVLPGB and TLBSYNC instruction supported
|
||||
KEYLOCKER // Key locker
|
||||
KEYLOCKERW // Key locker wide
|
||||
LAHF // LAHF/SAHF in long mode
|
||||
LAM // If set, CPU supports Linear Address Masking
|
||||
LBRVIRT // LBR virtualization
|
||||
LZCNT // LZCNT instruction
|
||||
MCAOVERFLOW // MCA overflow recovery support.
|
||||
MCDT_NO // Processor do not exhibit MXCSR Configuration Dependent Timing behavior and do not need to mitigate it.
|
||||
MCOMMIT // MCOMMIT instruction supported
|
||||
MD_CLEAR // VERW clears CPU buffers
|
||||
MMX // standard MMX
|
||||
MMXEXT // SSE integer functions or AMD MMX ext
|
||||
MOVBE // MOVBE instruction (big-endian)
|
||||
MOVDIR64B // Move 64 Bytes as Direct Store
|
||||
MOVDIRI // Move Doubleword as Direct Store
|
||||
MOVSB_ZL // Fast Zero-Length MOVSB
|
||||
MOVU // AMD: MOVU SSE instructions are more efficient and should be preferred to SSE MOVL/MOVH. MOVUPS is more efficient than MOVLPS/MOVHPS. MOVUPD is more efficient than MOVLPD/MOVHPD
|
||||
MPX // Intel MPX (Memory Protection Extensions)
|
||||
MSRIRC // Instruction Retired Counter MSR available
|
||||
MSRLIST // Read/Write List of Model Specific Registers
|
||||
MSR_PAGEFLUSH // Page Flush MSR available
|
||||
NRIPS // Indicates support for NRIP save on VMEXIT
|
||||
NX // NX (No-Execute) bit
|
||||
OSXSAVE // XSAVE enabled by OS
|
||||
PCONFIG // PCONFIG for Intel Multi-Key Total Memory Encryption
|
||||
POPCNT // POPCNT instruction
|
||||
PPIN // AMD: Protected Processor Inventory Number support. Indicates that Protected Processor Inventory Number (PPIN) capability can be enabled
|
||||
PREFETCHI // PREFETCHIT0/1 instructions
|
||||
PSFD // Predictive Store Forward Disable
|
||||
RDPRU // RDPRU instruction supported
|
||||
RDRAND // RDRAND instruction is available
|
||||
RDSEED // RDSEED instruction is available
|
||||
RDTSCP // RDTSCP Instruction
|
||||
RRSBA_CTRL // Restricted RSB Alternate
|
||||
RTM // Restricted Transactional Memory
|
||||
RTM_ALWAYS_ABORT // Indicates that the loaded microcode is forcing RTM abort.
|
||||
SBPB // Indicates support for the Selective Branch Predictor Barrier
|
||||
SERIALIZE // Serialize Instruction Execution
|
||||
SEV // AMD Secure Encrypted Virtualization supported
|
||||
SEV_64BIT // AMD SEV guest execution only allowed from a 64-bit host
|
||||
SEV_ALTERNATIVE // AMD SEV Alternate Injection supported
|
||||
SEV_DEBUGSWAP // Full debug state swap supported for SEV-ES guests
|
||||
SEV_ES // AMD SEV Encrypted State supported
|
||||
SEV_RESTRICTED // AMD SEV Restricted Injection supported
|
||||
SEV_SNP // AMD SEV Secure Nested Paging supported
|
||||
SGX // Software Guard Extensions
|
||||
SGXLC // Software Guard Extensions Launch Control
|
||||
SHA // Intel SHA Extensions
|
||||
SME // AMD Secure Memory Encryption supported
|
||||
SME_COHERENT // AMD Hardware cache coherency across encryption domains enforced
|
||||
SPEC_CTRL_SSBD // Speculative Store Bypass Disable
|
||||
SRBDS_CTRL // SRBDS mitigation MSR available
|
||||
SRSO_MSR_FIX // Indicates that software may use MSR BP_CFG[BpSpecReduce] to mitigate SRSO.
|
||||
SRSO_NO // Indicates the CPU is not subject to the SRSO vulnerability
|
||||
SRSO_USER_KERNEL_NO // Indicates the CPU is not subject to the SRSO vulnerability across user/kernel boundaries
|
||||
SSE // SSE functions
|
||||
SSE2 // P4 SSE functions
|
||||
SSE3 // Prescott SSE3 functions
|
||||
SSE4 // Penryn SSE4.1 functions
|
||||
SSE42 // Nehalem SSE4.2 functions
|
||||
SSE4A // AMD Barcelona microarchitecture SSE4a instructions
|
||||
SSSE3 // Conroe SSSE3 functions
|
||||
STIBP // Single Thread Indirect Branch Predictors
|
||||
STIBP_ALWAYSON // AMD: Single Thread Indirect Branch Prediction Mode has Enhanced Performance and may be left Always On
|
||||
STOSB_SHORT // Fast short STOSB
|
||||
SUCCOR // Software uncorrectable error containment and recovery capability.
|
||||
SVM // AMD Secure Virtual Machine
|
||||
SVMDA // Indicates support for the SVM decode assists.
|
||||
SVMFBASID // SVM, Indicates that TLB flush events, including CR3 writes and CR4.PGE toggles, flush only the current ASID's TLB entries. Also indicates support for the extended VMCBTLB_Control
|
||||
SVML // AMD SVM lock. Indicates support for SVM-Lock.
|
||||
SVMNP // AMD SVM nested paging
|
||||
SVMPF // SVM pause intercept filter. Indicates support for the pause intercept filter
|
||||
SVMPFT // SVM PAUSE filter threshold. Indicates support for the PAUSE filter cycle count threshold
|
||||
SYSCALL // System-Call Extension (SCE): SYSCALL and SYSRET instructions.
|
||||
SYSEE // SYSENTER and SYSEXIT instructions
|
||||
TBM // AMD Trailing Bit Manipulation
|
||||
TDX_GUEST // Intel Trust Domain Extensions Guest
|
||||
TLB_FLUSH_NESTED // AMD: Flushing includes all the nested translations for guest translations
|
||||
TME // Intel Total Memory Encryption. The following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE, IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE.
|
||||
TOPEXT // TopologyExtensions: topology extensions support. Indicates support for CPUID Fn8000_001D_EAX_x[N:0]-CPUID Fn8000_001E_EDX.
|
||||
TSCRATEMSR // MSR based TSC rate control. Indicates support for MSR TSC ratio MSRC000_0104
|
||||
TSXLDTRK // Intel TSX Suspend Load Address Tracking
|
||||
VAES // Vector AES. AVX(512) versions requires additional checks.
|
||||
VMCBCLEAN // VMCB clean bits. Indicates support for VMCB clean bits.
|
||||
VMPL // AMD VM Permission Levels supported
|
||||
VMSA_REGPROT // AMD VMSA Register Protection supported
|
||||
VMX // Virtual Machine Extensions
|
||||
VPCLMULQDQ // Carry-Less Multiplication Quadword. Requires AVX for 3 register versions.
|
||||
VTE // AMD Virtual Transparent Encryption supported
|
||||
WAITPKG // TPAUSE, UMONITOR, UMWAIT
|
||||
WBNOINVD // Write Back and Do Not Invalidate Cache
|
||||
WRMSRNS // Non-Serializing Write to Model Specific Register
|
||||
X87 // FPU
|
||||
XGETBV1 // Supports XGETBV with ECX = 1
|
||||
XOP // Bulldozer XOP functions
|
||||
XSAVE // XSAVE, XRESTOR, XSETBV, XGETBV
|
||||
XSAVEC // Supports XSAVEC and the compacted form of XRSTOR.
|
||||
XSAVEOPT // XSAVEOPT available
|
||||
XSAVES // Supports XSAVES/XRSTORS and IA32_XSS
|
||||
|
||||
// ARM features:
|
||||
AESARM // AES instructions
|
||||
@@ -296,9 +314,11 @@ type CPUInfo struct {
|
||||
L2 int // L2 Cache (per core or shared). Will be -1 if undetected
|
||||
L3 int // L3 Cache (per core, per ccx or shared). Will be -1 if undetected
|
||||
}
|
||||
SGX SGXSupport
|
||||
maxFunc uint32
|
||||
maxExFunc uint32
|
||||
SGX SGXSupport
|
||||
AMDMemEncryption AMDMemEncryptionSupport
|
||||
AVX10Level uint8
|
||||
maxFunc uint32
|
||||
maxExFunc uint32
|
||||
}
|
||||
|
||||
var cpuid func(op uint32) (eax, ebx, ecx, edx uint32)
|
||||
@@ -1065,6 +1085,32 @@ func hasSGX(available, lc bool) (rval SGXSupport) {
|
||||
return
|
||||
}
|
||||
|
||||
type AMDMemEncryptionSupport struct {
|
||||
Available bool
|
||||
CBitPossition uint32
|
||||
NumVMPL uint32
|
||||
PhysAddrReduction uint32
|
||||
NumEntryptedGuests uint32
|
||||
MinSevNoEsAsid uint32
|
||||
}
|
||||
|
||||
func hasAMDMemEncryption(available bool) (rval AMDMemEncryptionSupport) {
|
||||
rval.Available = available
|
||||
if !available {
|
||||
return
|
||||
}
|
||||
|
||||
_, b, c, d := cpuidex(0x8000001f, 0)
|
||||
|
||||
rval.CBitPossition = b & 0x3f
|
||||
rval.PhysAddrReduction = (b >> 6) & 0x3F
|
||||
rval.NumVMPL = (b >> 12) & 0xf
|
||||
rval.NumEntryptedGuests = c
|
||||
rval.MinSevNoEsAsid = d
|
||||
|
||||
return
|
||||
}
|
||||
|
||||
func support() flagSet {
|
||||
var fs flagSet
|
||||
mfi := maxFunctionID()
|
||||
@@ -1159,6 +1205,7 @@ func support() flagSet {
|
||||
fs.setIf(ecx&(1<<10) != 0, VPCLMULQDQ)
|
||||
fs.setIf(ecx&(1<<13) != 0, TME)
|
||||
fs.setIf(ecx&(1<<25) != 0, CLDEMOTE)
|
||||
fs.setIf(ecx&(1<<23) != 0, KEYLOCKER)
|
||||
fs.setIf(ecx&(1<<27) != 0, MOVDIRI)
|
||||
fs.setIf(ecx&(1<<28) != 0, MOVDIR64B)
|
||||
fs.setIf(ecx&(1<<29) != 0, ENQCMD)
|
||||
@@ -1181,13 +1228,8 @@ func support() flagSet {
|
||||
fs.setIf(edx&(1<<30) != 0, IA32_CORE_CAP)
|
||||
fs.setIf(edx&(1<<31) != 0, SPEC_CTRL_SSBD)
|
||||
|
||||
// CPUID.(EAX=7, ECX=1).EDX
|
||||
fs.setIf(edx&(1<<4) != 0, AVXVNNIINT8)
|
||||
fs.setIf(edx&(1<<5) != 0, AVXNECONVERT)
|
||||
fs.setIf(edx&(1<<14) != 0, PREFETCHI)
|
||||
|
||||
// CPUID.(EAX=7, ECX=1).EAX
|
||||
eax1, _, _, _ := cpuidex(7, 1)
|
||||
eax1, _, _, edx1 := cpuidex(7, 1)
|
||||
fs.setIf(fs.inSet(AVX) && eax1&(1<<4) != 0, AVXVNNI)
|
||||
fs.setIf(eax1&(1<<7) != 0, CMPCCXADD)
|
||||
fs.setIf(eax1&(1<<10) != 0, MOVSB_ZL)
|
||||
@@ -1197,6 +1239,13 @@ func support() flagSet {
|
||||
fs.setIf(eax1&(1<<23) != 0, AVXIFMA)
|
||||
fs.setIf(eax1&(1<<26) != 0, LAM)
|
||||
|
||||
// CPUID.(EAX=7, ECX=1).EDX
|
||||
fs.setIf(edx1&(1<<4) != 0, AVXVNNIINT8)
|
||||
fs.setIf(edx1&(1<<5) != 0, AVXNECONVERT)
|
||||
fs.setIf(edx1&(1<<14) != 0, PREFETCHI)
|
||||
fs.setIf(edx1&(1<<19) != 0, AVX10)
|
||||
fs.setIf(edx1&(1<<21) != 0, APX_F)
|
||||
|
||||
// Only detect AVX-512 features if XGETBV is supported
|
||||
if c&((1<<26)|(1<<27)) == (1<<26)|(1<<27) {
|
||||
// Check for OS support
|
||||
@@ -1232,13 +1281,33 @@ func support() flagSet {
|
||||
fs.setIf(edx&(1<<25) != 0, AMXINT8)
|
||||
// eax1 = CPUID.(EAX=7, ECX=1).EAX
|
||||
fs.setIf(eax1&(1<<5) != 0, AVX512BF16)
|
||||
fs.setIf(eax1&(1<<19) != 0, WRMSRNS)
|
||||
fs.setIf(eax1&(1<<21) != 0, AMXFP16)
|
||||
fs.setIf(eax1&(1<<27) != 0, MSRLIST)
|
||||
}
|
||||
}
|
||||
|
||||
// CPUID.(EAX=7, ECX=2)
|
||||
_, _, _, edx = cpuidex(7, 2)
|
||||
fs.setIf(edx&(1<<0) != 0, PSFD)
|
||||
fs.setIf(edx&(1<<1) != 0, IDPRED_CTRL)
|
||||
fs.setIf(edx&(1<<2) != 0, RRSBA_CTRL)
|
||||
fs.setIf(edx&(1<<4) != 0, BHI_CTRL)
|
||||
fs.setIf(edx&(1<<5) != 0, MCDT_NO)
|
||||
|
||||
// Add keylocker features.
|
||||
if fs.inSet(KEYLOCKER) && mfi >= 0x19 {
|
||||
_, ebx, _, _ := cpuidex(0x19, 0)
|
||||
fs.setIf(ebx&5 == 5, KEYLOCKERW) // Bit 0 and 2 (1+4)
|
||||
}
|
||||
|
||||
// Add AVX10 features.
|
||||
if fs.inSet(AVX10) && mfi >= 0x24 {
|
||||
_, ebx, _, _ := cpuidex(0x24, 0)
|
||||
fs.setIf(ebx&(1<<16) != 0, AVX10_128)
|
||||
fs.setIf(ebx&(1<<17) != 0, AVX10_256)
|
||||
fs.setIf(ebx&(1<<18) != 0, AVX10_512)
|
||||
}
|
||||
}
|
||||
|
||||
// Processor Extended State Enumeration Sub-leaf (EAX = 0DH, ECX = 1)
|
||||
@@ -1381,9 +1450,47 @@ func support() flagSet {
|
||||
fs.setIf((a>>24)&1 == 1, VMSA_REGPROT)
|
||||
}
|
||||
|
||||
if maxExtendedFunction() >= 0x80000021 && vend == AMD {
|
||||
a, _, _, _ := cpuid(0x80000021)
|
||||
fs.setIf((a>>31)&1 == 1, SRSO_MSR_FIX)
|
||||
fs.setIf((a>>30)&1 == 1, SRSO_USER_KERNEL_NO)
|
||||
fs.setIf((a>>29)&1 == 1, SRSO_NO)
|
||||
fs.setIf((a>>28)&1 == 1, IBPB_BRTYPE)
|
||||
fs.setIf((a>>27)&1 == 1, SBPB)
|
||||
}
|
||||
|
||||
if mfi >= 0x20 {
|
||||
// Microsoft has decided to purposefully hide the information
|
||||
// of the guest TEE when VMs are being created using Hyper-V.
|
||||
//
|
||||
// This leads us to check for the Hyper-V cpuid features
|
||||
// (0x4000000C), and then for the `ebx` value set.
|
||||
//
|
||||
// For Intel TDX, `ebx` is set as `0xbe3`, being 3 the part
|
||||
// we're mostly interested about,according to:
|
||||
// https://github.com/torvalds/linux/blob/d2f51b3516dade79269ff45eae2a7668ae711b25/arch/x86/include/asm/hyperv-tlfs.h#L169-L174
|
||||
_, ebx, _, _ := cpuid(0x4000000C)
|
||||
fs.setIf(ebx == 0xbe3, TDX_GUEST)
|
||||
}
|
||||
|
||||
if mfi >= 0x21 {
|
||||
// Intel Trusted Domain Extensions Guests have their own cpuid leaf (0x21).
|
||||
_, ebx, ecx, edx := cpuid(0x21)
|
||||
identity := string(valAsString(ebx, edx, ecx))
|
||||
fs.setIf(identity == "IntelTDX ", TDX_GUEST)
|
||||
}
|
||||
|
||||
return fs
|
||||
}
|
||||
|
||||
func (c *CPUInfo) supportAVX10() uint8 {
|
||||
if c.maxFunc >= 0x24 && c.featureSet.inSet(AVX10) {
|
||||
_, ebx, _, _ := cpuidex(0x24, 0)
|
||||
return uint8(ebx)
|
||||
}
|
||||
return 0
|
||||
}
|
||||
|
||||
func valAsString(values ...uint32) []byte {
|
||||
r := make([]byte, 4*len(values))
|
||||
for i, v := range values {
|
||||
|
||||
2
vendor/github.com/klauspost/cpuid/v2/detect_x86.go
generated
vendored
2
vendor/github.com/klauspost/cpuid/v2/detect_x86.go
generated
vendored
@@ -27,10 +27,12 @@ func addInfo(c *CPUInfo, safe bool) {
|
||||
c.Family, c.Model, c.Stepping = familyModel()
|
||||
c.featureSet = support()
|
||||
c.SGX = hasSGX(c.featureSet.inSet(SGX), c.featureSet.inSet(SGXLC))
|
||||
c.AMDMemEncryption = hasAMDMemEncryption(c.featureSet.inSet(SME) || c.featureSet.inSet(SEV))
|
||||
c.ThreadsPerCore = threadsPerCore()
|
||||
c.LogicalCores = logicalCores()
|
||||
c.PhysicalCores = physicalCores()
|
||||
c.VendorID, c.VendorString = vendorID()
|
||||
c.AVX10Level = c.supportAVX10()
|
||||
c.cacheSize()
|
||||
c.frequencies()
|
||||
}
|
||||
|
||||
406
vendor/github.com/klauspost/cpuid/v2/featureid_string.go
generated
vendored
406
vendor/github.com/klauspost/cpuid/v2/featureid_string.go
generated
vendored
@@ -16,204 +16,222 @@ func _() {
|
||||
_ = x[AMXFP16-6]
|
||||
_ = x[AMXINT8-7]
|
||||
_ = x[AMXTILE-8]
|
||||
_ = x[AVX-9]
|
||||
_ = x[AVX2-10]
|
||||
_ = x[AVX512BF16-11]
|
||||
_ = x[AVX512BITALG-12]
|
||||
_ = x[AVX512BW-13]
|
||||
_ = x[AVX512CD-14]
|
||||
_ = x[AVX512DQ-15]
|
||||
_ = x[AVX512ER-16]
|
||||
_ = x[AVX512F-17]
|
||||
_ = x[AVX512FP16-18]
|
||||
_ = x[AVX512IFMA-19]
|
||||
_ = x[AVX512PF-20]
|
||||
_ = x[AVX512VBMI-21]
|
||||
_ = x[AVX512VBMI2-22]
|
||||
_ = x[AVX512VL-23]
|
||||
_ = x[AVX512VNNI-24]
|
||||
_ = x[AVX512VP2INTERSECT-25]
|
||||
_ = x[AVX512VPOPCNTDQ-26]
|
||||
_ = x[AVXIFMA-27]
|
||||
_ = x[AVXNECONVERT-28]
|
||||
_ = x[AVXSLOW-29]
|
||||
_ = x[AVXVNNI-30]
|
||||
_ = x[AVXVNNIINT8-31]
|
||||
_ = x[BMI1-32]
|
||||
_ = x[BMI2-33]
|
||||
_ = x[CETIBT-34]
|
||||
_ = x[CETSS-35]
|
||||
_ = x[CLDEMOTE-36]
|
||||
_ = x[CLMUL-37]
|
||||
_ = x[CLZERO-38]
|
||||
_ = x[CMOV-39]
|
||||
_ = x[CMPCCXADD-40]
|
||||
_ = x[CMPSB_SCADBS_SHORT-41]
|
||||
_ = x[CMPXCHG8-42]
|
||||
_ = x[CPBOOST-43]
|
||||
_ = x[CPPC-44]
|
||||
_ = x[CX16-45]
|
||||
_ = x[EFER_LMSLE_UNS-46]
|
||||
_ = x[ENQCMD-47]
|
||||
_ = x[ERMS-48]
|
||||
_ = x[F16C-49]
|
||||
_ = x[FLUSH_L1D-50]
|
||||
_ = x[FMA3-51]
|
||||
_ = x[FMA4-52]
|
||||
_ = x[FP128-53]
|
||||
_ = x[FP256-54]
|
||||
_ = x[FSRM-55]
|
||||
_ = x[FXSR-56]
|
||||
_ = x[FXSROPT-57]
|
||||
_ = x[GFNI-58]
|
||||
_ = x[HLE-59]
|
||||
_ = x[HRESET-60]
|
||||
_ = x[HTT-61]
|
||||
_ = x[HWA-62]
|
||||
_ = x[HYBRID_CPU-63]
|
||||
_ = x[HYPERVISOR-64]
|
||||
_ = x[IA32_ARCH_CAP-65]
|
||||
_ = x[IA32_CORE_CAP-66]
|
||||
_ = x[IBPB-67]
|
||||
_ = x[IBRS-68]
|
||||
_ = x[IBRS_PREFERRED-69]
|
||||
_ = x[IBRS_PROVIDES_SMP-70]
|
||||
_ = x[IBS-71]
|
||||
_ = x[IBSBRNTRGT-72]
|
||||
_ = x[IBSFETCHSAM-73]
|
||||
_ = x[IBSFFV-74]
|
||||
_ = x[IBSOPCNT-75]
|
||||
_ = x[IBSOPCNTEXT-76]
|
||||
_ = x[IBSOPSAM-77]
|
||||
_ = x[IBSRDWROPCNT-78]
|
||||
_ = x[IBSRIPINVALIDCHK-79]
|
||||
_ = x[IBS_FETCH_CTLX-80]
|
||||
_ = x[IBS_OPDATA4-81]
|
||||
_ = x[IBS_OPFUSE-82]
|
||||
_ = x[IBS_PREVENTHOST-83]
|
||||
_ = x[IBS_ZEN4-84]
|
||||
_ = x[INT_WBINVD-85]
|
||||
_ = x[INVLPGB-86]
|
||||
_ = x[LAHF-87]
|
||||
_ = x[LAM-88]
|
||||
_ = x[LBRVIRT-89]
|
||||
_ = x[LZCNT-90]
|
||||
_ = x[MCAOVERFLOW-91]
|
||||
_ = x[MCDT_NO-92]
|
||||
_ = x[MCOMMIT-93]
|
||||
_ = x[MD_CLEAR-94]
|
||||
_ = x[MMX-95]
|
||||
_ = x[MMXEXT-96]
|
||||
_ = x[MOVBE-97]
|
||||
_ = x[MOVDIR64B-98]
|
||||
_ = x[MOVDIRI-99]
|
||||
_ = x[MOVSB_ZL-100]
|
||||
_ = x[MOVU-101]
|
||||
_ = x[MPX-102]
|
||||
_ = x[MSRIRC-103]
|
||||
_ = x[MSR_PAGEFLUSH-104]
|
||||
_ = x[NRIPS-105]
|
||||
_ = x[NX-106]
|
||||
_ = x[OSXSAVE-107]
|
||||
_ = x[PCONFIG-108]
|
||||
_ = x[POPCNT-109]
|
||||
_ = x[PPIN-110]
|
||||
_ = x[PREFETCHI-111]
|
||||
_ = x[PSFD-112]
|
||||
_ = x[RDPRU-113]
|
||||
_ = x[RDRAND-114]
|
||||
_ = x[RDSEED-115]
|
||||
_ = x[RDTSCP-116]
|
||||
_ = x[RTM-117]
|
||||
_ = x[RTM_ALWAYS_ABORT-118]
|
||||
_ = x[SERIALIZE-119]
|
||||
_ = x[SEV-120]
|
||||
_ = x[SEV_64BIT-121]
|
||||
_ = x[SEV_ALTERNATIVE-122]
|
||||
_ = x[SEV_DEBUGSWAP-123]
|
||||
_ = x[SEV_ES-124]
|
||||
_ = x[SEV_RESTRICTED-125]
|
||||
_ = x[SEV_SNP-126]
|
||||
_ = x[SGX-127]
|
||||
_ = x[SGXLC-128]
|
||||
_ = x[SHA-129]
|
||||
_ = x[SME-130]
|
||||
_ = x[SME_COHERENT-131]
|
||||
_ = x[SPEC_CTRL_SSBD-132]
|
||||
_ = x[SRBDS_CTRL-133]
|
||||
_ = x[SSE-134]
|
||||
_ = x[SSE2-135]
|
||||
_ = x[SSE3-136]
|
||||
_ = x[SSE4-137]
|
||||
_ = x[SSE42-138]
|
||||
_ = x[SSE4A-139]
|
||||
_ = x[SSSE3-140]
|
||||
_ = x[STIBP-141]
|
||||
_ = x[STIBP_ALWAYSON-142]
|
||||
_ = x[STOSB_SHORT-143]
|
||||
_ = x[SUCCOR-144]
|
||||
_ = x[SVM-145]
|
||||
_ = x[SVMDA-146]
|
||||
_ = x[SVMFBASID-147]
|
||||
_ = x[SVML-148]
|
||||
_ = x[SVMNP-149]
|
||||
_ = x[SVMPF-150]
|
||||
_ = x[SVMPFT-151]
|
||||
_ = x[SYSCALL-152]
|
||||
_ = x[SYSEE-153]
|
||||
_ = x[TBM-154]
|
||||
_ = x[TLB_FLUSH_NESTED-155]
|
||||
_ = x[TME-156]
|
||||
_ = x[TOPEXT-157]
|
||||
_ = x[TSCRATEMSR-158]
|
||||
_ = x[TSXLDTRK-159]
|
||||
_ = x[VAES-160]
|
||||
_ = x[VMCBCLEAN-161]
|
||||
_ = x[VMPL-162]
|
||||
_ = x[VMSA_REGPROT-163]
|
||||
_ = x[VMX-164]
|
||||
_ = x[VPCLMULQDQ-165]
|
||||
_ = x[VTE-166]
|
||||
_ = x[WAITPKG-167]
|
||||
_ = x[WBNOINVD-168]
|
||||
_ = x[X87-169]
|
||||
_ = x[XGETBV1-170]
|
||||
_ = x[XOP-171]
|
||||
_ = x[XSAVE-172]
|
||||
_ = x[XSAVEC-173]
|
||||
_ = x[XSAVEOPT-174]
|
||||
_ = x[XSAVES-175]
|
||||
_ = x[AESARM-176]
|
||||
_ = x[ARMCPUID-177]
|
||||
_ = x[ASIMD-178]
|
||||
_ = x[ASIMDDP-179]
|
||||
_ = x[ASIMDHP-180]
|
||||
_ = x[ASIMDRDM-181]
|
||||
_ = x[ATOMICS-182]
|
||||
_ = x[CRC32-183]
|
||||
_ = x[DCPOP-184]
|
||||
_ = x[EVTSTRM-185]
|
||||
_ = x[FCMA-186]
|
||||
_ = x[FP-187]
|
||||
_ = x[FPHP-188]
|
||||
_ = x[GPA-189]
|
||||
_ = x[JSCVT-190]
|
||||
_ = x[LRCPC-191]
|
||||
_ = x[PMULL-192]
|
||||
_ = x[SHA1-193]
|
||||
_ = x[SHA2-194]
|
||||
_ = x[SHA3-195]
|
||||
_ = x[SHA512-196]
|
||||
_ = x[SM3-197]
|
||||
_ = x[SM4-198]
|
||||
_ = x[SVE-199]
|
||||
_ = x[lastID-200]
|
||||
_ = x[APX_F-9]
|
||||
_ = x[AVX-10]
|
||||
_ = x[AVX10-11]
|
||||
_ = x[AVX10_128-12]
|
||||
_ = x[AVX10_256-13]
|
||||
_ = x[AVX10_512-14]
|
||||
_ = x[AVX2-15]
|
||||
_ = x[AVX512BF16-16]
|
||||
_ = x[AVX512BITALG-17]
|
||||
_ = x[AVX512BW-18]
|
||||
_ = x[AVX512CD-19]
|
||||
_ = x[AVX512DQ-20]
|
||||
_ = x[AVX512ER-21]
|
||||
_ = x[AVX512F-22]
|
||||
_ = x[AVX512FP16-23]
|
||||
_ = x[AVX512IFMA-24]
|
||||
_ = x[AVX512PF-25]
|
||||
_ = x[AVX512VBMI-26]
|
||||
_ = x[AVX512VBMI2-27]
|
||||
_ = x[AVX512VL-28]
|
||||
_ = x[AVX512VNNI-29]
|
||||
_ = x[AVX512VP2INTERSECT-30]
|
||||
_ = x[AVX512VPOPCNTDQ-31]
|
||||
_ = x[AVXIFMA-32]
|
||||
_ = x[AVXNECONVERT-33]
|
||||
_ = x[AVXSLOW-34]
|
||||
_ = x[AVXVNNI-35]
|
||||
_ = x[AVXVNNIINT8-36]
|
||||
_ = x[BHI_CTRL-37]
|
||||
_ = x[BMI1-38]
|
||||
_ = x[BMI2-39]
|
||||
_ = x[CETIBT-40]
|
||||
_ = x[CETSS-41]
|
||||
_ = x[CLDEMOTE-42]
|
||||
_ = x[CLMUL-43]
|
||||
_ = x[CLZERO-44]
|
||||
_ = x[CMOV-45]
|
||||
_ = x[CMPCCXADD-46]
|
||||
_ = x[CMPSB_SCADBS_SHORT-47]
|
||||
_ = x[CMPXCHG8-48]
|
||||
_ = x[CPBOOST-49]
|
||||
_ = x[CPPC-50]
|
||||
_ = x[CX16-51]
|
||||
_ = x[EFER_LMSLE_UNS-52]
|
||||
_ = x[ENQCMD-53]
|
||||
_ = x[ERMS-54]
|
||||
_ = x[F16C-55]
|
||||
_ = x[FLUSH_L1D-56]
|
||||
_ = x[FMA3-57]
|
||||
_ = x[FMA4-58]
|
||||
_ = x[FP128-59]
|
||||
_ = x[FP256-60]
|
||||
_ = x[FSRM-61]
|
||||
_ = x[FXSR-62]
|
||||
_ = x[FXSROPT-63]
|
||||
_ = x[GFNI-64]
|
||||
_ = x[HLE-65]
|
||||
_ = x[HRESET-66]
|
||||
_ = x[HTT-67]
|
||||
_ = x[HWA-68]
|
||||
_ = x[HYBRID_CPU-69]
|
||||
_ = x[HYPERVISOR-70]
|
||||
_ = x[IA32_ARCH_CAP-71]
|
||||
_ = x[IA32_CORE_CAP-72]
|
||||
_ = x[IBPB-73]
|
||||
_ = x[IBPB_BRTYPE-74]
|
||||
_ = x[IBRS-75]
|
||||
_ = x[IBRS_PREFERRED-76]
|
||||
_ = x[IBRS_PROVIDES_SMP-77]
|
||||
_ = x[IBS-78]
|
||||
_ = x[IBSBRNTRGT-79]
|
||||
_ = x[IBSFETCHSAM-80]
|
||||
_ = x[IBSFFV-81]
|
||||
_ = x[IBSOPCNT-82]
|
||||
_ = x[IBSOPCNTEXT-83]
|
||||
_ = x[IBSOPSAM-84]
|
||||
_ = x[IBSRDWROPCNT-85]
|
||||
_ = x[IBSRIPINVALIDCHK-86]
|
||||
_ = x[IBS_FETCH_CTLX-87]
|
||||
_ = x[IBS_OPDATA4-88]
|
||||
_ = x[IBS_OPFUSE-89]
|
||||
_ = x[IBS_PREVENTHOST-90]
|
||||
_ = x[IBS_ZEN4-91]
|
||||
_ = x[IDPRED_CTRL-92]
|
||||
_ = x[INT_WBINVD-93]
|
||||
_ = x[INVLPGB-94]
|
||||
_ = x[KEYLOCKER-95]
|
||||
_ = x[KEYLOCKERW-96]
|
||||
_ = x[LAHF-97]
|
||||
_ = x[LAM-98]
|
||||
_ = x[LBRVIRT-99]
|
||||
_ = x[LZCNT-100]
|
||||
_ = x[MCAOVERFLOW-101]
|
||||
_ = x[MCDT_NO-102]
|
||||
_ = x[MCOMMIT-103]
|
||||
_ = x[MD_CLEAR-104]
|
||||
_ = x[MMX-105]
|
||||
_ = x[MMXEXT-106]
|
||||
_ = x[MOVBE-107]
|
||||
_ = x[MOVDIR64B-108]
|
||||
_ = x[MOVDIRI-109]
|
||||
_ = x[MOVSB_ZL-110]
|
||||
_ = x[MOVU-111]
|
||||
_ = x[MPX-112]
|
||||
_ = x[MSRIRC-113]
|
||||
_ = x[MSRLIST-114]
|
||||
_ = x[MSR_PAGEFLUSH-115]
|
||||
_ = x[NRIPS-116]
|
||||
_ = x[NX-117]
|
||||
_ = x[OSXSAVE-118]
|
||||
_ = x[PCONFIG-119]
|
||||
_ = x[POPCNT-120]
|
||||
_ = x[PPIN-121]
|
||||
_ = x[PREFETCHI-122]
|
||||
_ = x[PSFD-123]
|
||||
_ = x[RDPRU-124]
|
||||
_ = x[RDRAND-125]
|
||||
_ = x[RDSEED-126]
|
||||
_ = x[RDTSCP-127]
|
||||
_ = x[RRSBA_CTRL-128]
|
||||
_ = x[RTM-129]
|
||||
_ = x[RTM_ALWAYS_ABORT-130]
|
||||
_ = x[SBPB-131]
|
||||
_ = x[SERIALIZE-132]
|
||||
_ = x[SEV-133]
|
||||
_ = x[SEV_64BIT-134]
|
||||
_ = x[SEV_ALTERNATIVE-135]
|
||||
_ = x[SEV_DEBUGSWAP-136]
|
||||
_ = x[SEV_ES-137]
|
||||
_ = x[SEV_RESTRICTED-138]
|
||||
_ = x[SEV_SNP-139]
|
||||
_ = x[SGX-140]
|
||||
_ = x[SGXLC-141]
|
||||
_ = x[SHA-142]
|
||||
_ = x[SME-143]
|
||||
_ = x[SME_COHERENT-144]
|
||||
_ = x[SPEC_CTRL_SSBD-145]
|
||||
_ = x[SRBDS_CTRL-146]
|
||||
_ = x[SRSO_MSR_FIX-147]
|
||||
_ = x[SRSO_NO-148]
|
||||
_ = x[SRSO_USER_KERNEL_NO-149]
|
||||
_ = x[SSE-150]
|
||||
_ = x[SSE2-151]
|
||||
_ = x[SSE3-152]
|
||||
_ = x[SSE4-153]
|
||||
_ = x[SSE42-154]
|
||||
_ = x[SSE4A-155]
|
||||
_ = x[SSSE3-156]
|
||||
_ = x[STIBP-157]
|
||||
_ = x[STIBP_ALWAYSON-158]
|
||||
_ = x[STOSB_SHORT-159]
|
||||
_ = x[SUCCOR-160]
|
||||
_ = x[SVM-161]
|
||||
_ = x[SVMDA-162]
|
||||
_ = x[SVMFBASID-163]
|
||||
_ = x[SVML-164]
|
||||
_ = x[SVMNP-165]
|
||||
_ = x[SVMPF-166]
|
||||
_ = x[SVMPFT-167]
|
||||
_ = x[SYSCALL-168]
|
||||
_ = x[SYSEE-169]
|
||||
_ = x[TBM-170]
|
||||
_ = x[TDX_GUEST-171]
|
||||
_ = x[TLB_FLUSH_NESTED-172]
|
||||
_ = x[TME-173]
|
||||
_ = x[TOPEXT-174]
|
||||
_ = x[TSCRATEMSR-175]
|
||||
_ = x[TSXLDTRK-176]
|
||||
_ = x[VAES-177]
|
||||
_ = x[VMCBCLEAN-178]
|
||||
_ = x[VMPL-179]
|
||||
_ = x[VMSA_REGPROT-180]
|
||||
_ = x[VMX-181]
|
||||
_ = x[VPCLMULQDQ-182]
|
||||
_ = x[VTE-183]
|
||||
_ = x[WAITPKG-184]
|
||||
_ = x[WBNOINVD-185]
|
||||
_ = x[WRMSRNS-186]
|
||||
_ = x[X87-187]
|
||||
_ = x[XGETBV1-188]
|
||||
_ = x[XOP-189]
|
||||
_ = x[XSAVE-190]
|
||||
_ = x[XSAVEC-191]
|
||||
_ = x[XSAVEOPT-192]
|
||||
_ = x[XSAVES-193]
|
||||
_ = x[AESARM-194]
|
||||
_ = x[ARMCPUID-195]
|
||||
_ = x[ASIMD-196]
|
||||
_ = x[ASIMDDP-197]
|
||||
_ = x[ASIMDHP-198]
|
||||
_ = x[ASIMDRDM-199]
|
||||
_ = x[ATOMICS-200]
|
||||
_ = x[CRC32-201]
|
||||
_ = x[DCPOP-202]
|
||||
_ = x[EVTSTRM-203]
|
||||
_ = x[FCMA-204]
|
||||
_ = x[FP-205]
|
||||
_ = x[FPHP-206]
|
||||
_ = x[GPA-207]
|
||||
_ = x[JSCVT-208]
|
||||
_ = x[LRCPC-209]
|
||||
_ = x[PMULL-210]
|
||||
_ = x[SHA1-211]
|
||||
_ = x[SHA2-212]
|
||||
_ = x[SHA3-213]
|
||||
_ = x[SHA512-214]
|
||||
_ = x[SM3-215]
|
||||
_ = x[SM4-216]
|
||||
_ = x[SVE-217]
|
||||
_ = x[lastID-218]
|
||||
_ = x[firstID-0]
|
||||
}
|
||||
|
||||
const _FeatureID_name = "firstIDADXAESNIAMD3DNOWAMD3DNOWEXTAMXBF16AMXFP16AMXINT8AMXTILEAVXAVX2AVX512BF16AVX512BITALGAVX512BWAVX512CDAVX512DQAVX512ERAVX512FAVX512FP16AVX512IFMAAVX512PFAVX512VBMIAVX512VBMI2AVX512VLAVX512VNNIAVX512VP2INTERSECTAVX512VPOPCNTDQAVXIFMAAVXNECONVERTAVXSLOWAVXVNNIAVXVNNIINT8BMI1BMI2CETIBTCETSSCLDEMOTECLMULCLZEROCMOVCMPCCXADDCMPSB_SCADBS_SHORTCMPXCHG8CPBOOSTCPPCCX16EFER_LMSLE_UNSENQCMDERMSF16CFLUSH_L1DFMA3FMA4FP128FP256FSRMFXSRFXSROPTGFNIHLEHRESETHTTHWAHYBRID_CPUHYPERVISORIA32_ARCH_CAPIA32_CORE_CAPIBPBIBRSIBRS_PREFERREDIBRS_PROVIDES_SMPIBSIBSBRNTRGTIBSFETCHSAMIBSFFVIBSOPCNTIBSOPCNTEXTIBSOPSAMIBSRDWROPCNTIBSRIPINVALIDCHKIBS_FETCH_CTLXIBS_OPDATA4IBS_OPFUSEIBS_PREVENTHOSTIBS_ZEN4INT_WBINVDINVLPGBLAHFLAMLBRVIRTLZCNTMCAOVERFLOWMCDT_NOMCOMMITMD_CLEARMMXMMXEXTMOVBEMOVDIR64BMOVDIRIMOVSB_ZLMOVUMPXMSRIRCMSR_PAGEFLUSHNRIPSNXOSXSAVEPCONFIGPOPCNTPPINPREFETCHIPSFDRDPRURDRANDRDSEEDRDTSCPRTMRTM_ALWAYS_ABORTSERIALIZESEVSEV_64BITSEV_ALTERNATIVESEV_DEBUGSWAPSEV_ESSEV_RESTRICTEDSEV_SNPSGXSGXLCSHASMESME_COHERENTSPEC_CTRL_SSBDSRBDS_CTRLSSESSE2SSE3SSE4SSE42SSE4ASSSE3STIBPSTIBP_ALWAYSONSTOSB_SHORTSUCCORSVMSVMDASVMFBASIDSVMLSVMNPSVMPFSVMPFTSYSCALLSYSEETBMTLB_FLUSH_NESTEDTMETOPEXTTSCRATEMSRTSXLDTRKVAESVMCBCLEANVMPLVMSA_REGPROTVMXVPCLMULQDQVTEWAITPKGWBNOINVDX87XGETBV1XOPXSAVEXSAVECXSAVEOPTXSAVESAESARMARMCPUIDASIMDASIMDDPASIMDHPASIMDRDMATOMICSCRC32DCPOPEVTSTRMFCMAFPFPHPGPAJSCVTLRCPCPMULLSHA1SHA2SHA3SHA512SM3SM4SVElastID"
|
||||
const _FeatureID_name = "firstIDADXAESNIAMD3DNOWAMD3DNOWEXTAMXBF16AMXFP16AMXINT8AMXTILEAPX_FAVXAVX10AVX10_128AVX10_256AVX10_512AVX2AVX512BF16AVX512BITALGAVX512BWAVX512CDAVX512DQAVX512ERAVX512FAVX512FP16AVX512IFMAAVX512PFAVX512VBMIAVX512VBMI2AVX512VLAVX512VNNIAVX512VP2INTERSECTAVX512VPOPCNTDQAVXIFMAAVXNECONVERTAVXSLOWAVXVNNIAVXVNNIINT8BHI_CTRLBMI1BMI2CETIBTCETSSCLDEMOTECLMULCLZEROCMOVCMPCCXADDCMPSB_SCADBS_SHORTCMPXCHG8CPBOOSTCPPCCX16EFER_LMSLE_UNSENQCMDERMSF16CFLUSH_L1DFMA3FMA4FP128FP256FSRMFXSRFXSROPTGFNIHLEHRESETHTTHWAHYBRID_CPUHYPERVISORIA32_ARCH_CAPIA32_CORE_CAPIBPBIBPB_BRTYPEIBRSIBRS_PREFERREDIBRS_PROVIDES_SMPIBSIBSBRNTRGTIBSFETCHSAMIBSFFVIBSOPCNTIBSOPCNTEXTIBSOPSAMIBSRDWROPCNTIBSRIPINVALIDCHKIBS_FETCH_CTLXIBS_OPDATA4IBS_OPFUSEIBS_PREVENTHOSTIBS_ZEN4IDPRED_CTRLINT_WBINVDINVLPGBKEYLOCKERKEYLOCKERWLAHFLAMLBRVIRTLZCNTMCAOVERFLOWMCDT_NOMCOMMITMD_CLEARMMXMMXEXTMOVBEMOVDIR64BMOVDIRIMOVSB_ZLMOVUMPXMSRIRCMSRLISTMSR_PAGEFLUSHNRIPSNXOSXSAVEPCONFIGPOPCNTPPINPREFETCHIPSFDRDPRURDRANDRDSEEDRDTSCPRRSBA_CTRLRTMRTM_ALWAYS_ABORTSBPBSERIALIZESEVSEV_64BITSEV_ALTERNATIVESEV_DEBUGSWAPSEV_ESSEV_RESTRICTEDSEV_SNPSGXSGXLCSHASMESME_COHERENTSPEC_CTRL_SSBDSRBDS_CTRLSRSO_MSR_FIXSRSO_NOSRSO_USER_KERNEL_NOSSESSE2SSE3SSE4SSE42SSE4ASSSE3STIBPSTIBP_ALWAYSONSTOSB_SHORTSUCCORSVMSVMDASVMFBASIDSVMLSVMNPSVMPFSVMPFTSYSCALLSYSEETBMTDX_GUESTTLB_FLUSH_NESTEDTMETOPEXTTSCRATEMSRTSXLDTRKVAESVMCBCLEANVMPLVMSA_REGPROTVMXVPCLMULQDQVTEWAITPKGWBNOINVDWRMSRNSX87XGETBV1XOPXSAVEXSAVECXSAVEOPTXSAVESAESARMARMCPUIDASIMDASIMDDPASIMDHPASIMDRDMATOMICSCRC32DCPOPEVTSTRMFCMAFPFPHPGPAJSCVTLRCPCPMULLSHA1SHA2SHA3SHA512SM3SM4SVElastID"
|
||||
|
||||
var _FeatureID_index = [...]uint16{0, 7, 10, 15, 23, 34, 41, 48, 55, 62, 65, 69, 79, 91, 99, 107, 115, 123, 130, 140, 150, 158, 168, 179, 187, 197, 215, 230, 237, 249, 256, 263, 274, 278, 282, 288, 293, 301, 306, 312, 316, 325, 343, 351, 358, 362, 366, 380, 386, 390, 394, 403, 407, 411, 416, 421, 425, 429, 436, 440, 443, 449, 452, 455, 465, 475, 488, 501, 505, 509, 523, 540, 543, 553, 564, 570, 578, 589, 597, 609, 625, 639, 650, 660, 675, 683, 693, 700, 704, 707, 714, 719, 730, 737, 744, 752, 755, 761, 766, 775, 782, 790, 794, 797, 803, 816, 821, 823, 830, 837, 843, 847, 856, 860, 865, 871, 877, 883, 886, 902, 911, 914, 923, 938, 951, 957, 971, 978, 981, 986, 989, 992, 1004, 1018, 1028, 1031, 1035, 1039, 1043, 1048, 1053, 1058, 1063, 1077, 1088, 1094, 1097, 1102, 1111, 1115, 1120, 1125, 1131, 1138, 1143, 1146, 1162, 1165, 1171, 1181, 1189, 1193, 1202, 1206, 1218, 1221, 1231, 1234, 1241, 1249, 1252, 1259, 1262, 1267, 1273, 1281, 1287, 1293, 1301, 1306, 1313, 1320, 1328, 1335, 1340, 1345, 1352, 1356, 1358, 1362, 1365, 1370, 1375, 1380, 1384, 1388, 1392, 1398, 1401, 1404, 1407, 1413}
|
||||
var _FeatureID_index = [...]uint16{0, 7, 10, 15, 23, 34, 41, 48, 55, 62, 67, 70, 75, 84, 93, 102, 106, 116, 128, 136, 144, 152, 160, 167, 177, 187, 195, 205, 216, 224, 234, 252, 267, 274, 286, 293, 300, 311, 319, 323, 327, 333, 338, 346, 351, 357, 361, 370, 388, 396, 403, 407, 411, 425, 431, 435, 439, 448, 452, 456, 461, 466, 470, 474, 481, 485, 488, 494, 497, 500, 510, 520, 533, 546, 550, 561, 565, 579, 596, 599, 609, 620, 626, 634, 645, 653, 665, 681, 695, 706, 716, 731, 739, 750, 760, 767, 776, 786, 790, 793, 800, 805, 816, 823, 830, 838, 841, 847, 852, 861, 868, 876, 880, 883, 889, 896, 909, 914, 916, 923, 930, 936, 940, 949, 953, 958, 964, 970, 976, 986, 989, 1005, 1009, 1018, 1021, 1030, 1045, 1058, 1064, 1078, 1085, 1088, 1093, 1096, 1099, 1111, 1125, 1135, 1147, 1154, 1173, 1176, 1180, 1184, 1188, 1193, 1198, 1203, 1208, 1222, 1233, 1239, 1242, 1247, 1256, 1260, 1265, 1270, 1276, 1283, 1288, 1291, 1300, 1316, 1319, 1325, 1335, 1343, 1347, 1356, 1360, 1372, 1375, 1385, 1388, 1395, 1403, 1410, 1413, 1420, 1423, 1428, 1434, 1442, 1448, 1454, 1462, 1467, 1474, 1481, 1489, 1496, 1501, 1506, 1513, 1517, 1519, 1523, 1526, 1531, 1536, 1541, 1545, 1549, 1553, 1559, 1562, 1565, 1568, 1574}
|
||||
|
||||
func (i FeatureID) String() string {
|
||||
if i < 0 || i >= FeatureID(len(_FeatureID_index)-1) {
|
||||
|
||||
Reference in New Issue
Block a user